In many jurisdictions it is desirable to provide for processing of digital video data signals in different formats in the same video signal processing unit. Such video signal processing units, in general are implemented in the form of one or more signal processing integrated circuit chips. However, whether the video signal processing unit is provided with one or more signal processing chips, in general it is necessary that the video data signals in the different formats be processed simultaneously. Implementing a video signal processing unit in the form of a number of signal processing chips lends itself more readily to simultaneous processing of different format video data signals, than do implementations which include only one single video signal processing chip. Although, video signal processing chips capable of simultaneous processing of different format video data signals are known, however, in general, since the various different format video data signals are clocked by different clock signals, separate clock signals are required for processing the respective different format video data signals. This leads to duplication of frequency multipliers which are required for multiplying the frequency of the clock signals for Interpolation of the video data signals. A separate frequency multiplier is required for each format video data signal. Since frequency multipliers tend to require a relatively large die area in an integrated circuit, excessive die area is, in general, required to accommodate the frequency multipliers.
In general, the three most common video data signal formats are standard definition format, progressive scan format and high definition format. The standard definition format is also referred to as interlace data format. In general, video data signals in standard definition are clocked at 13.5 Hz, while video data signals in progressive scan format are clocked at 27 MHz. High definition format video data signals are clocked at a higher frequency of 74.25 Mhz. However, these frequencies may vary. Indeed, it is known to have standard definition format signals clocked at frequencies between 12 MHz and 14.75 MHz, while progressive scan format signals may be clocked at frequencies of up to 29 MHz. The clock frequency for high definition format signals can range between 70 MHz and 82 MHz. Standard definition format signals may be provided in any of the following standards PAL, NTSC and SECAM, progressive scan format signals may be provided in 525P and 625P standards, while high definition format signals may be provided in 1010I, 720P and 1250I standards.
Accordingly, where a video signal processing unit is implemented as a single chip which comprises separate processing circuits, one for processing the video data signals of standard definition, another for processing video data signals in progressive scan and a third processing circuit for processing high definition format video data signals a separate clock multiplier circuit is required for each video signal processing circuit.
While the clock signals of standard definition and progressive scan format appear to be of different frequency, in general, the standard definition format clock signal can be brought up to an identical frequency to that of the progressive scan clock signal, although a phase difference may exist between the two identical clock frequencies. This phase difference, however, remains constant. However, because of the fact that the clock signals of the respective standard definition and progressive scan format video data signals are out of phase, separate frequency multiplying circuitry is required for multiplying the respective clock frequencies of the clock signals of the respective standard definition and progressive scan video signals in the respective video data signal processing circuits for interpolating the video data signals. This is inconvenient, and as discussed above leads to additional die area, which in turn leads to additional expense in the production and fabrication of such integrated circuit chips. The problem is particularly critical where it is desired to provide a single integrated circuit chip with processing circuitry for standard definition format signals and processing circuitry for progressive scan format video data signals, since in such cases die area is at a premium, and the requirement to provide separate frequency multiplying circuits for multiplying the clock frequencies of the respective clock signal for facilitating processing of the respective format video data signals in the respective video data signal processing circuits is particularly problematical.
There is therefore a need for a method for processing respective first and second digital video data signals which are clocked by respective first and second clock signals of identical frequency and having a constant phase relationship, and in particular, there is a need for a method which facilitates simultaneous processing of standard definition and progressive scan digital video data signal using a single clock signal. There is also a need for a video signal processor for processing respective first and second digital video data signals which are clocked by respective first and second clock signals of identical frequency and having a constant phase relationship, and in particular, there is a need for such a video signal processor which facilitates simultaneous processing of the standard definition and progressive scan digital video data signal using a single clock signal.
The present invention is directed towards providing such a method and a video signal processor.